Friday, December 5, 2014

What is an EMC Design Review?

Andy Eadie

Note: This blog post was edited and reproduced with permission from EMC FastPass. EMC FastPass helps manufacturers get to market cheaper and faster with design review software and online EMC/RF video training courses.



What is an EMC Design Review?

Most hardware engineers are used to doing functional design reviews on their circuit boards and systems before pressing the 'go' button for manufacturing. In the engineering teams I've worked with, that type of design review has usually taken the form of standing around a board room table with a red pen and the largest print outs of the schematics that we could get our hands on. It can also be done by just one person at a PC with cross probing enabled between schematics and layout (if your boss was kind enough to get that license!). We sifted through the design, pin by pin and connector by connector, determined to find an accidentally reversed interface or incorrectly pinned out symbol. You knew that there was a good chance that the schematics in front of you contained a hidden mistake that had the potential to turn your high end circuit board into an expensive beer coaster, or cost you a lot of rework time at the least!

Companies that are on the ball have standardized this kind of review process into a checklist based procedure that is run through and verified on each and every design. By doing this, they increase the robustness of the review and minimize the chances of a major issue slipping through the cracks.

Surprisingly, very few companies that I've been involved with over the years have migrated this important process into the EMC world. In just the same way that a functional design review can catch many design errors, a solid EMC design review can catch lots of known poor design practices for emissions and immunity performance. It can mean the difference between your product passing or failing at an EMC test lab.

A good EMC design review should cover many aspects of an overall product design. At the top level, a design review should cover topics such as:



EMC as a Functional Specification

I like to think of EMC testing as a completely separate functional specification. There are a specific set of pass/fail criteria that your product must meet, or you can't sell it. It's that simple. Without a clear specification of the tests your product is going to be subjected to at an EMC lab, you are lacking a functional specification that should really be taken into account at the design stage of your project. You wouldn't dream of designing a product without a clear view of the feature set being provided to the end customer would you? EMC testing is a just a different kind of feature set that your design needs to include. Without an EMC functional specification, you're leaving a pass or fail at an EMC lab up to chance. Is it any coincidence then, that according to Intertek (one of the largest lab groups in the world), the global EMC first time pass rate is only 50%?

In this post I'm going to give an overview of what an EMC design review is and how to go about doing one on your next product.

Why Bother to do an EMC Design Review?
An EMC failure can very easily cost your company several thousand dollars in tangible expenses such as hiring a consultant, renting debug equipment, re-working/manufacturing designs and paying for re-tests. A larger concern for many companies is the delay to market that an EMC failure can cause. Since EMC approval is required before you can legally sell your product, a failure can introduce a delay to market of several days to several weeks. The longest delay to market that I've come across due to an EMC failure is about 4 months as the company really struggled to solve the issues through several design iterations, but I wouldn't be surprised if longer delays exist.

Accountants generally agree that a delay to market will reduce the peak sales volume of any given product by a few percent and depending on the nature of your product, may reduce the length of the overall sales window. For many medium to large hardware companies, a 1 month delay can easily lead to a reduction in overall revenue for a particular product during its' lifespan of greater than $1 million. Suddenly, considering EMC early in the design cycle doesn't look like a bad idea at all.

Lastly, doing a robust EMC design review can increase the performance of your product and therefore reduce the number of customer returns. For example, a company that has a product with relatively poor immunity protection may get lots of returns due to damage from static discharges coming from the end user's fingers when they're pushing buttons on the product. Or perhaps the product will be used in a relatively noisy electromagnetic environment and the functioning of the device is affected in some ways such as degradation of RF performance or measurement accuracy. Good EMC design can reduce these sorts of issues.

Companies who are lucky enough to have an EMC expert on staff may not have implemented a robust EMC design review (yet), but the knowledge locked away in the expert's head is probably already introducing an ad hoc review of sorts. What I've noticed is that design engineers who have significant experience with EMC testing tend to use their memory of EMC failure modes to avoid running into the same issues again in the future. For example, as they're laying out a circuit board (or directing a draftsman), they may remember a time when a previous product they designed failed radiated emissions due to excessive noise on the external cabling. The engineer then takes whatever design improvement they implemented to reduce the noise on the cabling and applies that methodology to all designs in the future. What they've essentially done is to build up a set of design rules that they follow for each successive design. As they experience more EMC issues and solve them, they add these rules to their existing mental list.

Standardizing these rules into formal design review procedure is key to repeatedly performing a robust EMC design review. Companies such as Ford and Jaguar who face some of the toughest EMC challenges (automotive) implement robust EMC design reviews. I believe everyone can benefit from taking this approach. One huge benefit of a formalized EMC design review is that it can be undertaken by a relatively junior engineer without much experience in design for EMC compliance. This is because it's much easier to check that a specific design rule has been implemented correctly than it is to do comprehensive EMC training and understand why a rule makes sense from a physics perspective. For companies without a seasoned EMC pro on staff, an EMC design review is a great way to quickly verify that your design has the best chance of passing EMC testing.

Unfortunately, most companies do not have a skilled EMC engineer on staff and do not have the in house knowledge to create an EMC design review process. EMC training is usually incredibly expensive, with typical pricing for a short 2-3 day seminar of >$1500 USD plus expenses per engineer.

I can't go into every single item covered in a comprehensive EMC design review, but in this post I'm going to detail a few of the most important aspects that I always check. The section below gives you a top level overview of how I do EMC design reviews for clients.

How to Get Started
Define your Pass/Fail Specifications

Without a clear definition of the pass/fail criteria, you don't have a good specification to work with. In some cases, your product may only be tested for radiated and conducted emissions performance. In others, your product may also be subjected to immunity phenomena such as ESD, surge and EFT. The first task is to detail the limits and levels for emissions and immunity that your product must achieve during EMC testing.

Emissions Limits
First, you should define what the emission limits are for your product. These may vary depending on the environment that your product will be used in and the regions of the world where it will be sold. One of the most important places to start is to work out whether your product falls under "Class A" or "Class B" limits. Here's how the FCC makes the distinction:

Class A digital device: A digital device that is marketed for use in a commercial, industrial or business environment, exclusive of a device which is marketed for use by the general public or is intended to be used in the home.
Class B digital device: A digital device that is marketed for use in a residential environment notwithstanding use in commercial, business and industrial environments. Examples of such devices include, but are not limited to, personal computers, calculators, and similar electronic devices that are marketed for use by the general public.

It's important to note that Class B limits are significantly lower than Class A limits.

Limits also differ between geographic region and between product types. Check the standards that apply to your product (or ask a test lab) to work out the limits that you're going to need to meet.


I've included an example below of some limits for a class B unintentional emitting device so that you can see what it looks like. The lower and upper frequencies covered by the limits vary depending on the internal clock frequencies present within your product and also vary depending on the standards that apply to your product.

Although you can get a feel for the radiated emissions from particular nets in your design using free tools like the 'Maximum Emission Calculator' tool from Clemson university, it isn't very practical to use tools like this for analyzing a full design. Emission limits typically cover radiated and conducted emissions as well as Ethernet conducted emissions (if applicable).

Finding out the emission limits that apply to your particular product gives you a good idea of how difficult it's going to be to get your product's emissions below the limits.

Immunity Levels and Pass/Fail Criteria
If immunity testing applies to your product (usually mandatory for CE Mark and global product family standards), then it's worth finding out what test levels an EMC lab is going to use, where the tests will be applied and how well your product needs to perform during and after the test (this is called performance criteria). This will help you to work out where to apply EMC suppression devices, what ratings to choose and will also give you an idea of how much care you need to take. If you have a regular test lab that you use, they should be happy to provide you with a test plan up front so that you can use it in the design stage of your product development cycle. If you have a relationship with a test lab, they should be willing to help you. If they're not, it might be time to start looking for a different test lab.

You can see an example of an immunity test plan below, which includes the levels that will be applied to your product and the criteria that your product needs to meet.
 

The definition of the pass/fail criteria can vary a bit from standard to standard, but here is a description of each performance criteria taken from the international generic immunity standard for residential, commercial and light-industrial environments (IEC 61000-6-1):

a) Performance criterion A: The apparatus shall continue to operate as intended during and after the test. No degradation of performance or loss of function is allowed below a performance level specified by the manufacturer, when the apparatus is used as intended. The performance level may be replaced by a permissible loss of performance. If the minimum performance level or the permissible performance loss is not specified by the manufacturer, either of these may be derived from the product description and documentation and what the user may reasonably expect from the apparatus if used as intended.

b) Performance criterion B: The apparatus shall continue to operate as intended after the test. No degradation of performance or loss of function is allowed below a performance level specified by the manufacturer, when the apparatus is used as intended. The performance level may be replaced by a permissible loss of performance. During the test, degradation of performance is however allowed. No change of actual operating state or stored data is allowed. If the minimum performance level or the permissible performance loss is not specified by the manufacturer, either of these may be derived from the product description and documentation and what the user may reasonably expect from the apparatus if used as intended.

c) Performance criterion C: Temporary loss of function is allowed, provided the function is self-recoverable or can be restored by the operation of the controls.
It's essential to find out the performance criteria that your product will have to meet at a test lab.
Emissions

1. Pick the right stack-up


Configuring the right PCB stack is fundamental to EMC performance. Without an adequate layer count for a given complexity and without the correct layer order and usage, you're going to make your job of controlling radiated and conducted emissions pretty hard. If your boss is pushing you to reduce the layer count to save on PCB costs, just remember that there is usually a trade off with EMC performance, which has the potential to hurt the company wallet even more.

The desirable features of a good PCB stack (from an EMC perspective) are:
• Signal layers adjacent to plane layers
• Signal layers tightly coupled to return power/ground plane
• Power and grounds closely coupled
• High speed signals on buried layers
• Symmetrical

With those features in mind, here are sample layer stacks for 4 and 6 layer boards:

4 Layer Example Stack



In this diagram you can see a couple of different ways that 4 layer stacks can be implemented. See if you can work out from the desirable characteristics listed above, what the trade offs are for each stack.

6 Layer Example Stack


Can you work out why the stack on the left is not recommended?

I don't have time to cover it here, but the stack geometry and PCB materials can also heavily affect EMC performance. That's because it will define the impedance of nets and planes which can vary from layer to layer. Without careful consideration of the board impedance, you can run in to significant signal integrity and power delivery network (PDN) problems.

2. Does every IC have adequate de-coupling?

This one is repeated a lot, but it's worth verifying and confirming during an EMC design review that every single IC has adequate decoupling. When I do EMC design reviews for clients, I usually find at least a couple of ICs or PWR/GND pin pairs where the designer forgot to add de-coupling caps or the caps have been implemented in a way that would make them pretty ineffective. You can see the effect of adding de-coupling to an IC below (reproduced with permission from Williamson Labs).

The upper left diagram shows the effect of de-coupling on supply noise in the frequency domain and the upper right diagram shows the effect in the time domain. You can see that the optimal performance is when the decoupling cap is place below the IC and routed as directly as possible between the PWR and GND pin pair.


It's worth noting that the important characteristics of decoupling capacitors include not only the value of the capacitor (nF, pF etc) but also ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance). This EDN blog post does a good job of explaining the effect of those characteristics on PDN impedance.

3. Check for breaks in the return path

If you're not familiar with return paths, it just means the route current flows back to the source. Whenever you have an IC that supplies current to another device, there is an equal and opposite current that travels back to the source device.


The diagram above illustrates that the return path in DC travels the path of least resistance. The return path in AC (higher frequency signals) travels the path of least inductance, which is usually on a reference plane directly underneath the source signal. Whenever there is a cut in the return path on the reference plane, the return current has to flow around the cut to find the path of least inductance. This forms a nice current loop that has the potential to become an efficient radiator.

The diagram below shows a 0.5 GHz signal that traverses a cut in the ground plane. You can see in the right hand picture that the current distribution on the return path finds a way around the slot and therefore makes a loop. The left hand picture shows a scenario where the cuts in the return path have been bridged by capacitors which allow the high frequency return current to 'jump' over the gaps.


The effect on far field radiated emissions from this one signal might surprise you. The simulation of this scenario shows that emissions measured at 10 metres from this net alone can be more than 30 dB higher with a cut in the return plane. This can definitely mean the difference between a pass or fail at an EMC lab.


[Source unknown]

During an EMC design review, you should view your layout 2 layers at a time and carefully verify that all of your digital signals have a well defined return paths without cuts. If a cut in the return path is necessary for any reason, then ensure that the cuts have been bridged with capacitors that have low impedance at the frequencies of interest.

Immunity

1. Has ESD protection been applied to all external ports?

Once you know which ports of your product will be tested, you can add the ports to your EMC design review checklist. Now go and verify that each of the ports has adequate ESD protection on the circuit board, in the right places and of the correct rating. Here is an example of a USB port that has good ESD protection (from Texas Instruments).


Note that the protection should be placed as physically close to the port connector as possible. Many different types of ESD protection devices are available. Check out the ESD section in the "Getting EMC Design Right First Time" eBook for more details.

Closely related to this item is to verify that net to net clearances and and net to plane clearances near the ESD injection points do not allow for 'arcing'. This is to ensure that the ESD can't jump to another conductor and potentially cause damage elsewhere in the product. The suggested clearances required to ensure that arcs do not occur for given voltage levels in various circumstances are covered in the IPC-2221 standard.

2. Sensitive Circuitry Shielding


Radiated immunity is a very common test that applies to most electronic devices destined for Europe, or those that adhere to international product standards. The field strengths that your product may be subjected to can vary between 1V/m and 200 V/m depending on the standard. The field is also usually swept across the frequency range 80 MHz - 4 GHz (some standards may go higher and lower than this).


If your product contains sensitive circuitry such as analog measurement circuits or RF circuitry, then even low power radiated electric fields can introduce major issues. A common and inexpensive way to protect circuitry from radiated fields is to provide a small shield over the circuitry of interest.

A few simple checks that I do during an EMC design review are:
• Are there any circuit elements that are likely to be susceptible to radiated electric fields?
• Is shield grounded at multiple points?
• Is shield fitted tightly to PCB?
• Check solder joints are not dry
• Are apertures (e.g. for ventilation) in the shield minimized?
• If apertures are required, are they positioned at furthest point away from sensitive circuitry?

Note that shielding alone often isn't enough to immunize your sensitive circuitry from radiated electric fields. Often the field is picked up by external cabling and is coupled on to a circuit board. Once that energy is on the circuit board, it can affect the sensitive circuitry by things like voltage fluctuations on the ground or power planes. The EMC Design Review Pro software goes into much more depth regarding radiated immunity, covering items like bandwidth limiting, sensitive net considerations and inter nal cabling to name a few.

Tuesday, November 18, 2014

The Diagnosis of Under-Performing Semi-Anechoic Chamber Designs


As mentioned in the upcoming article ‘Applying Stealth Technology to EMC Chamber Designs’, and also mentioned during the recent EMC-LIVE webinar ‘Elephants in the TestRoom,’ the intention is to use 3D EM simulation software to explore possible design improvements to today’s under- performing chambers.

The article itself is not out yet, but we can make useful progress in the meantime by exploring the performance of the present ‘hot-wall’ arrangement. The hot-wall is the absorber clad wall behind the RF immunity calibration plane, and currently test labs are forced to point the antenna at a corner of the chamber to achieve test field compliance. Later on we will explore hot-wall wave-deflection (angled faces) as a possible design improvement.

Thanks are due to CST for the loan of their CST Studio Suite® 2014 Software, and particular thanks are due to Dr. Andreas Barchanski of CST for helping with the modelling and analysis.

IN THE BEGINNING

As with any engineering project, before any engineering time is invested, it pays to be sure of the required outcome, and have a direction of attack.

Well, the first objective is to establish why it is so difficult to obtain field uniformity at the calibration plane with the present hot-wall design, so I propose our direction of attack is to gather information on the performance of a standard flat absorber clad wall. I further propose we establish the individual performance of each type of absorber (pyramidal and ferrite tile).

GETTING STARTED

We will start with an analysis of the pyramidal absorber performance. As stated above, we first need to be clear on what we want the software to do and how we want it to do it.


Figure 1 shows a side view of a single pyramidal absorber. It is made from carbon loaded dissipative material shaped to form an impedance taper. We want to examine it’s two-way wave attenuation performance, so there is a fully reflective PEC (perfect electrical conductor) sheet covering the surface of the pyramid base. The pyramid is designed to face the wave it is intended to attenuate directly, so we will get the software to strike it with a plane wave at normal incidence and make a relative measurement of the ‘echo’.

A field probe positioned to the left of the pyramid will see both the incident and reflected waves, so I suggest we use a trick of the trade. In RF engineering, if you want to establish the loss (unwanted copper and dielectric loss) in say a four-way combiner, one approach is to manufacture two of them, connect them back-to-back (connect four connectors to the other four connectors), and  measure the overall loss. Half that loss and you have the loss of one combiner.

We can use a similar approach with the pyramid absorber by placing two of them back-to-back as shown in Figure 2. We then place one field probe on the left and one on the right and measure the fields in isolation. We lose the 180 degree phase change caused by the reflective sheet (we will need to remember this), but we gain data on the reduction of the magnitude of the ‘echo’ wave.

 









Figure 3 and Figure 4 show the same approach used for a non-normal angle of incidence.


 



















ANTICIPATED RESULTS














It is good practice to anticipate the results so you can use them in a sanity check later.

Figure 5 shows the plane wave about to strike the absorber. The vertically polarized RF waveform is represented by colored arrows showing the direction and strength of the field along one wavelength. Starting from the right and working left, the arrows show the upward pointing field of the first half-cycle gaining in strength to its peak (red), then falling in strength for the remainder of the half cycle, and then repeating this variation in strength for the downward pointing field of the second half-cycle. The upward pointing arrow on the right will impinge on the absorber first.



 










Figure 6 shows the anticipated results. For clarity only the effect on the peaks of the wave are shown. The right hand arrow in the pyramid represents the first half-cycle peak as it travels though the absorber. The center of the arrow has passed furthest through the pyramid lossy material and so that segment is attenuated the most (now green). Segments above and below the center have travelled different distances and so display different levels of attenuation. The left hand arrow has not travelled as far and only the center segment (orange) has dropped in field strength up to that point in the pyramid.

EARLY RESULTS

Well, the anticipated results went straight out the window because the actual results were a complete and utter surprise.

Figure 7 shows a still shot of the animated simulation results. When the animation is run, blocks of concentric field-rings march left to right in much the same way as the satellite view of a hurricane making its way West to East over the Gulf of Mexico.
It is mesmerizing to watch. Hopefully the EMC-Zone editorial staff can arrange for readers to witness the animation on-line.

They say there is nothing new under the sun and the effect may have been predicted/observed by some great scientist (Fresnel or another), but until we know what they are, and for the purposes of this EMC-Zone discussion alone, we will christen the blocks of concentric rings ‘Eddy Field Blocks’ (EFBs).

Even if turns they only occur over a comparatively narrow frequency band, or due to slowing of the wave (dielectric constant of pyramid material holding carbon in suspension not equal to 1), they are absolutely fascinating to observe. Anyone out there know a meteorologist or someone familiar with fluid dynamics that has seen these type of circular fields before? I know vortices form in fast moving rivers etc, but these seem quite different (no spiral swirl to the center).














ROUGH DESCRIPTION

Initial observation suggests:-

An EFB begins to form inside and outside the material at the apex of the pyramid.

The EFBs are created at the apex every half-cycle of the incident wave, and dissipate at the base of the pyramid at the same rate.

EFBs are made up of concentric field rings, each ring pointing in the same direction, each ring remaining separate from the others within the eddy block.

Adjacent EFBs have field rings pointing in the opposite direction (clockwise or anti-clockwise).

The diameter of the EFBs is about ¼ wavelength of the incident wave.

The created EFB moves to the right and then pauses for the time it takes ¼ wavelength of the incident wave to pass. The EFB creation rate and dissipation rate are still the same (one every half cycle of the incident wave).

The EFB seems to be an entity in its own right, evidenced by continuing to exist while an incident wave minimum passes past it during the time the EFB pauses.

To be continued............

-Tom Mullineaux

Monday, October 27, 2014

Elephants in the Test Room Roundtable Commentary 1


On Thursday, Oct. 16, Interference Technology hosted a roundtable during EMC Live - 'Elephants in the Test Room' based on our blog series. Below is additional commentary about testing issues, from our expert panel.

Panel
Tom Mullineaux - Moderator, Consultant and Author
Patrick Andre - President, André Consulting, Inc.
Fin O'Connor - Defense and Space Consultant and Contractor, Alion Science and Technology
Adiseshu Nyshadham - Senior Consultant, DVT Solutions Inc.
Steve Koster - Vice President, Washington Labs






Elephants discussion points:

Elephant Discussion #1 – Poor EMC Measurement Consistency
No one is surprised when a round robin test shows multiple EMC testhouse measurements taken under supposedly identical test conditions are up to 10dB apart. By its nature, the ISO17025 laboratory accreditation standard covers a very broad church of test situations. However, the EMC industry is a distinct, identifiable niche. The various compliance groups providing the audit-service should be able to work together to improve inter-EMC laboratory measurement accuracy.

Can the EMC industry work with ISO17025 laboratory accreditation teams to improve measurement consistency?


Elephant Discussion #2 – Underperforming EMC Chambers
When calibrating a test field to 6GHz for commercial RF immunity testing, to obtain a compliant test field many test houses are finding they are forced to point the antenna at one corner of the room. All standard 3 meter semi-anechoic test chambers are cuboids with flat walls, ceiling and floor. The four walls and the ceiling are clad in RF absorber. The ‘hot’ wall (the one behind the calibration plane) performs the same as the other three walls.

Is a flat absorber lined ‘hot’ wall truly the only possibility?


Elephant Discussion #3 – Automotive Tests that Put the Car Audio System Performance First
Until fairly recently it seemed the RF immunity tests conducted inside the car cabin space were purely to ensure good sound system performance.

What is the future of RF immunity tests that actually check for electronic sub assembly compatibility inside the cabin space of a car?

DISCUSSION:

Patrick: 
Q. Can the EMC industry work with ISO17025 laboratory accreditation teams to improve measurement consistency?
A. Yes, improvements can always be made. However the challenge will be to first establish repeatability in a single test setup for each chamber. Often, changes of ±4 dB is seen with the most minor of test setup changes. The movement of a cable or the position of the support equipment can radically alter the results. Added to this the difficulty of different laboratory layouts, with different sized rooms, anechoic material differences, antenna configurations (both type and location), power line and signal line routings into and out of the room, to name a few, and soon you have so many variables between two so-called “identical setups” that getting only 10 dB differences is actually remarkably good.
Q. It might be necessary to introduce the use of a fully anechoic chamber where the floor is now covered with absorber, reducing at least one variable in the measurements.
A. All standard test chambers are cuboids with flat walls, ceiling and floor. Is this shape truly the only possibility?
Of course not. Reverberant chambers are already being made with non-parallel walls. Also, simply adding a metal or anechoic panel at a 45 degree angle in a corner can alter the fields significantly. However, I am somewhat surprised by the difficulties the labs have, since the cone style of anechoic material should work remarkably well at these frequencies.

Fin:
Boy, the #1 could go on for days!! I’m on the 461 committee and we will not have any uncertainties in the spec (ever as some say) the uncertainties are built into the limits. Now the test problem differences are very difficult to get a handle on. I travel to many independent and gov labs witnessing testing for NAVAIR and the differences in the way these test houses INTERPRET the standard is surprising. I am trying to get more description for each test into the ‘G’ version of the standard (which we are working on now) but I am getting resistance because they feel the standard has enough description for the competent engineer/tech. I was also involved, years ago, with the round robin testing for the NVLAP Mutual recognition project and this was a for the very simple open filed testing with specific parameters. And even with this test control, the differences between the test houses was 10 + db at least. I would love to see some way to get the testing differences smaller so anything that can be suggested and proven would be welcome but it’s a uphill road.

Patrick:
I think Fin and I are in violent agreement. As a fan of MIL-STD 461 and DO-160 (mainly due to my aerospace background), I love the fact that cable length and positions are defined and controlled (1 meter, 2 meters, 3.3 meters, and so forth, depending on the test and standard). Cables are placed on 5 cm standoffs, 10 cm from the front of the ground plane. And even then, even with all this control, we get these variations.
I am working on a piece of medical equipment, with five transducers, five monitors, plus peripheral and support equipment. How do I ever lay out the cables and support equipment the same so I can get the same results twice? I have seen 5 dB swings just moving one cable.
I think the only science less accurate than ours is Astronomy, where they state distances of remote objects within a couple decades, e.g. 10^6 to 10^8 light-years away. And I wanted to be an Astronomer.
Then again, I have had no success convincing the police officer of the accuracy of my speedometer. He just doesn’t buy the idea that as long as I am between 6 MPH and 600 MPH I am within the range of accuracy.

Tom:
Just to make sure you are up to speed with where the elephants are history wise, you should read the article I wrote recently for ITEM.
http://www.interferencetechnology.com/a-design-review-of-the-automotive-radiated-emissions-test-fixture/
In the article I am very critical of the design of the emissions test fixture. I have just received 3D EM software from CST so I can come up with a superior arrangement. Might have preliminary results in time for our webinar. But you should know that if you praise the 5cm high cable over a ground plane I am likely to lambast you without mercy, and have supporting data to do it with.

Fin:
Oh no, not a 5 cm debate. I’m always interested in why the specs are the way they are. I will be real interested in your research, and will pass on to the committee,if it will make the readings better. But being honest, we have been using this method for the longest and our planes fly, missiles find there mark and radios work, in theater/hostile environments and we have feedback from the fleet and we track problems and why they occur (NAVAIR has the ASEMICAP group which tracks fleet problems and finds the reason and solutions) so to get the community to change, you will have to have a really good reason. But sometimes change is good!! Just hard to get through.

Tom:
Yes, the long history and the fact that planes are not falling out of the sky speaks volumes. Hard to argue with physics though, particularly the possible mismatch between the noise source (EUT) and the test fixture.

Fin:
Tom, ‘test fixture’?? Not sure what you mean? The 5 cm is to closely resemble the common actual installation (Military environment, loop impedances), to get some consistency and to work with the LISN (below 10 MHz). Unfortunately though, as Patrick had, most of the time, the set-up is a mess and standardization is mostly impossible so these controls are the best comprise we have. But, like I’ve said before, suggestions are welcome, at least by me!

Patrick:
I agree with Fin completely.
A story I was told about 5 cm standoffs: I was doing testing at Celect, a division of Cincinnati Electronics, in the early ‘90’s with a man named John Day. When I made a comment about 5 cm standoffs, he stated that he may have had something to do with the fact they are a bit inconvenient. He told me that in the early days of military EMC emissions, someone thought that it would be a good idea make sure the cables are not laying directly on the copper bench, so they grabbed 2x4’s and put the cables onto them (which are 4 cm high). However, once things needed to be documented, and they were converting to metric, John was asked to go measure the height of the cables off the ground plane in centimeters. When he reported the measurement, he reported the height of the cable, which was a large cable bundle, and had measured to the center of the cable – which added 1 cm to the overall height.
He said the next thing he saw was a document stating the cables needed to be on standoffs 5 cm high based on the past tests. And he did not correct it.
Or this could just be a story he told me.

Fin:
FYI, some history . I knew Ken would have the lowdown. He has a pretty good museum of old equipment and books on EMI. And a pic of some of our old generators!!
Fin,
The answer involves some heavy math.
The first part of the heavy math is if one picture is worth a thousand words, how much is two pictures worth?
The first pic shows a radio room in a WW II-era bomber. On the left is the radio, on the right the unshielded antenna lead from the radio is visible held above aircraft structure via porcelain standoffs, to minimize capacitive loading of the high impedance signal.
The second pic shows the standoff dimension, in inches.
The rest of the heavy math is the conversion to MKS, which is left as an exercise for the reader...
- Ken Javor


Patrick:
Oh, of course. And I should have known Ken would know.
And I kinda figured John Day was handing me a line. Kinda.
Thanks! This is great stuff.

To be continued........

For more information on the roundtable, visit EMC Live's website here.